1. Field of the Invention
The present invention relates to data processing systems, and more particularly to data processing systems including one or more processors, and one or more input/output channel controllers, wherein the system has a plurality of clock timing signals.
2. Prior Art
Input/output channel controllers ("IOCC") are normally used in computer systems to generate industry standard input/output buses from high performance system/memory buses. These IOCCs typically contain large arrays for temporarily storing data as well as multiple clock signals to access or update dam.
These prior art systems present fundamental problems in achieving acceptable chip cycle times. First, standard array designs require that the array address and array write enables be valid and stable during the clock "active" time, i.e. "high" level or "low" level based on array design. For ease of understanding, this invention assumes the clock "active" time to be the "low" level. This means that the array address and array write enables must stabilize in less than one-half of the total clock cycle time, due to the clock "active" setup time requirements and variations in the clock duty cycle. Second, these arrays have significant hold time requirements, and most IOCC chip designs aggravate this problem with the use of multiple gated clocks to update the array.
A prior art method to solve the hold time problem was to add a fixed delay to the array address and array write enable signals. However, adding these delays reduces the critical half cycle path during the next cycle. Further, such delays would require a significant amount of hardware to delay these array inputs.